In integrated circuit (IC) fabrications, a patterned photoresist layer is used to transfer a designed pattern having small feature sizes from a photomask to a wafer. As resolution of patterns increases, it is desirable to shrink the critical dimension of photoresist patterns to create smaller feature sizes, However, there is currently a limit on how much the critical dimension of a photoresist pattern may be shrunk by post development treatments.
Therefore, there is need for a post development, treatment material and a lithography method to address the above issue.